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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. ? 2001 mos integrated circuit mc-222262-x mcp (multi-chip package) flash memory and sram 32m-bit flash memory and 8m-bit sram data sheet document no. m14923ej4v0ds00 (4th edition) date published march 2002 ns cp (k) printed in japan the mark shows major revised points. description the mc-222262-x is a stacked type mcp (multi-chip package) of 33,554,432 bits (byte mode : 4,194,304 words by 8 bits, word mode : 2,097,152 words by 16 bits) flash memory and 8,388,608 bits (byte mode : 1,048,576 words by 8 bits, word mode : 524,288 words by 16 bits) static ram. the mc-222262-x is packaged in a 77-pin tape fbga. features general features ? fast access time : t acc = 85 ns (max.) (flash memory), t aa = 70 ns (max.) (sram) ? supply voltage : v cc f / v cc s = 2.7 to 3.6 v ? wide operating temperature : t a = ? 25 to +85 c flash memory features ? two bank organization enabling simultaneous execution of program / erase and read ? bank organization : 2 banks (4m bits + 28m bits) ? memory organization : 4,194,304 words 8 bits (byte mode) 2,097,152 words 16 bits (word mode) ? sector organization : 71 sectors (8k bytes / 4k words 8 sectors, 64k bytes / 32k words 63 sectors) ? boot sector allocated to the highest address (sector) ? 3-state output ? automatic program ? program suspend / resume ? unlock bypass program ? automatic erase ? chip erase ? sector erase (sectors can be combined freely) ? erase suspend / resume ? program / erase completion detection ? detection through data polling and toggle bits ? detection through ry (/by) pin ? sector group protection ? any sector can be protected ? any protected sector can be temporary unprotected ? sectors can be used for boot application ? hardware reset and standby using /reset pin ? automatic sleep mode ? boot block sector protect by /wp (acc) pin ? conforms to common flash memory interface (cfi) ? extra one time protect sector provided sram features ? memory organization : 1,048,576 words 8 bits (byte mode) 524,288 words 16 bits (word mode) ? supply current : at operating : 50 ma (max.) at standby : 15 a (max.) ? two chip enable inputs : /ce1s, ce2s ? byte data select : /lb, /ub ? byte / word mode select : cios ? low v cc data retention : 1.0 to 3.6 v
data sheet m14923ej4v0ds 2 mc-222262-x ordering information part number flash memory flash memory sram package boot sector access time access time ns (max.) ns (max.) MC-222262F9-B85X-BT3 top address (sector) 85 70 77-pin tape fbga (12 7) (t type)
data sheet m14923ej4v0ds 3 mc-222262-x pin configuration /xxx indicates active low si gnal. 77-pin tape fbga (12 7) top view v ss i/o9 i/o5 a7 /oe i/o7 i/o4 i/o0 a6 a18 a11 a8 a5 i/o8 i/o12 a13 a17 sa /cef i/o10 v cc f /we v cc s a16 i/o11 ry(/by) /reset a12 i/o6 i/o13 a9 a15 a19 i/o14 /ce1s i/o15, a-1 i/o1 a1 a2 a4 a10 cios i/o2 a0 a3 ce2s a20 a14 /lb ciof /wp(acc) /ub i/o3 nc nc v ss top view bottom view 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 pnmlkjhgfedcba abcdefghjklmnp abcdefghjklmnp nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc common pins a0 - a18 : address inputs i/o0 - i/o15 : data inputs / outputs /oe : output enable /we : write enable v ss : ground nc note : no connection flash memory pins a19, a20 : address inputs i/o15, a ? 1 : data inputs / outputs 15 (word mode) lsb address input (byte mode) /cef : chip enable ry (/by) : ready (busy) output /reset : hardware reset input v cc f : supply voltage /wp(acc) : hardware write protect (acceleration) ciof : selects 8-bit or 16-bit mode sram pins sa : address input (a19 for sram) /ce1s : chip enable 1 ce2s : chip enable 2 v cc s : supply voltage /lb, /ub : byte data select cios : selects 8-bit or 16-bit mode note some signals can be applied because this pin is not internally connected. remark refer to package drawing for the index mark.
data sheet m14923ej4v0ds 4 mc-222262-x block diagram 32 m-bit flash memory 4,194,304 words by 8 bits 2,097,152 words by 16 bits sa /we /oe /ce1s /reset /cef i/o0 - i/o15, a-1 a0 - a20 8 m-bit sram 1,048,576 words by 8 bits 524,288 words by 16 bits ry (/by) a0 - a18 a0 - a20 v cc f v ss v cc s v ss ce2s /lb /ub cios ciof /wp(acc)
data sheet m14923ej4v0ds 5 mc-222262-x bus operations table operation flash memory sram common /reset /cef ciof /wp(acc) /ce1 s ce2 s /lb /ub cios /oe /we i/o0 - i/o7 i/o8-i/o15 full standby h h h hi-z hi-z l hh output disable h l lh h h hi-z hi-z read (flash byte mode h l l note 2 l h data out hi-z memory note 1 ) word mode h data out data out write (flash byte mode h l l note 2 h l data in hi-z memory) word mode h data in data in temporary sector group v id note 2 hi-z or hi-z or unprotect data in/out data in/out boot block sector protect l hi-z or data in/out hi-z or data in/out flash memory hardware reset l hi-z hi-z read (sram) byte mode note 3 lh l l h data out hi-z word mode note 3 l h l l h l h data out data out hhi-z h l hi-z data out write (sram) byte mode note 3 lh l l data in hi-z word mode note 3 lhllh l data in data in hhi-z h l hi-z data in caution other operations except for indicated in this table are inhibited. notes 1. when /oe = v il , v il can be applied to /we. when /oe = v ih , a write operation is started. 2. sram should be standby. 3. flash memory should be standby or hardware reset. remarks 1. : v ih or v il , h: v ih , l: v il 2. sector group protection and read the product id are using a command. 3. refer to dual operation flash memory 32m bits a series information (m14914e) for bus operations of flash memory. !
data sheet m14923ej4v0ds 6 mc-222262-x sector organization / sector address table (flash memory) flash memory top boot (1/2) bank sector address sectors sector address table organization address bank address table k bytes / k words byte mode word mode a20 a19 a18 a17 a16 a15 a14 a13 a12 bank 1 8/4 3fffffh 1fffffh fsa70 111111111 3fe000h 1ff000h 8/4 3fdfffh 1fefffh fsa69 111111110 3fc000h 1fe000h 8/4 3fbfffh 1fdfffh fsa68 111111101 3fa000h 1fd000h 8/4 3f9fffh 1fcfffh fsa67 111111100 3f8000h 1fc000h 8/4 3f7fffh 1fbfffh fsa66 111111011 3f6000h 1fb000h 8/4 3f5fffh 1fafffh fsa65 111111010 3f4000h 1fa000h 8/4 3f3fffh 1f9fffh fsa64 111111001 3f2000h 1f9000h 8/4 3f1fffh 1f8fffh fsa63 111111000 3f0000h 1f8000h 64/32 3effffh 1f7fffh fsa62 111110xxx 3e0000h 1f0000h 64/32 3dffffh 1effffh fsa61 111101xxx 3d0000h 1e8000h 64/32 3cffffh 1e7fffh fsa60 111100xxx 3c0000h 1e0000h 64/32 3bffffh 1dffffh fsa59 111011xxx 3b0000h 1d8000h 64/32 3affffh 1d7fffh fsa58 111010xxx 3a0000h 1d0000h 64/32 39ffffh 1cffffh fsa57 111001xxx 390000h 1c8000h 64/32 38ffffh 1c7fffh fsa56 111000xxx 380000h 1c0000h bank 2 64/32 37ffffh 1bffffh fsa55 110111xxx 370000h 1b8000h 64/32 36ffffh 1b7fffh fsa54 110110xxx 360000h 1b0000h 64/32 35ffffh 1affffh fsa53 110101xxx 350000h 1a8000h 64/32 34ffffh 1a7fffh fsa52 110100xxx 340000h 1a0000h 64/32 33ffffh 19ffffh fsa51 110011xxx 330000h 198000h 64/32 32ffffh 197fffh fsa50 110010xxx 320000h 190000h 64/32 31ffffh 18ffffh fsa49 110001xxx 310000h 188000h 64/32 30ffffh 187fffh fsa48 110000xxx 300000h 180000h 64/32 2fffffh 17ffffh fsa47 101111xxx 2f0000h 178000h 64/32 2effffh 177fffh fsa46 101110xxx 2e0000h 170000h 64/32 2dffffh 16ffffh fsa45 101101xxx 2d0000h 168000h 64/32 2cffffh 167fffh fsa44 101100xxx 2c0000h 160000h 64/32 2bffffh 15ffffh fsa43 101011xxx 2b0000h 158000h 64/32 2affffh 157fffh fsa42 101010xxx 2a0000h 150000h 64/32 29ffffh 14ffffh fsa41 101001xxx 290000h 148000h 64/32 28ffffh 147fffh fsa40 101000xxx 280000h 140000h 64/32 27ffffh 13ffffh fsa39 100111xxx 270000h 138000h 64/32 26ffffh 137fffh fsa38 100110xxx 260000h 130000h 64/32 25ffffh 12ffffh fsa37 100101xxx 250000h 128000h 64/32 24ffffh 127fffh fsa36 100100xxx 240000h 120000h 64/32 23ffffh 11ffffh fsa35 100011xxx 230000h 118000h
data sheet m14923ej4v0ds 7 mc-222262-x (2/2) bank sector address sectors sector address table organization address bank address table k bytes / k words byte mode word mode a20 a19 a18 a17 a16 a15 a14 a13 a12 bank 2 64/32 22ffffh 117fffh fsa34 100010xxx 220000h 110000h 64/32 21ffffh 10ffffh fsa33 100001xxx 210000h 108000h 64/32 20ffffh 107fffh fsa32 100000xxx 200000h 100000h 64/32 1fffffh 0fffffh fsa31 011111xxx 1f0000h 0f8000h 64/32 1effffh 0f7fffh fsa30 011110xxx 1e0000h 0f0000h 64/32 1dffffh 0effffh fsa29 011101xxx 1d0000h 0e8000h 64/32 1cffffh 0e7fffh fsa28 011100xxx 1c0000h 0e0000h 64/32 1bffffh 0dffffh fsa27 011011xxx 1b0000h 0d8000h 64/32 1affffh 0d7fffh fsa26 011010xxx 1a0000h 0d0000h 64/32 19ffffh 0cffffh fsa25 011001xxx 190000h 0c8000h 64/32 18ffffh 0c7fffh fsa24 011000xxx 180000h 0c0000h 64/32 17ffffh 0bffffh fsa23 010111xxx 170000h 0b8000h 64/32 16ffffh 0b7fffh fsa22 010110xxx 160000h 0b0000h 64/32 15ffffh 0affffh fsa21 010101xxx 150000h 0a8000h 64/32 14ffffh 0a7fffh fsa20 010100xxx 140000h 0a0000h 64/32 13ffffh 09ffffh fsa19 010011xxx 130000h 098000h 64/32 12ffffh 097fffh fsa18 010010xxx 120000h 090000h 64/32 11ffffh 08ffffh fsa17 010001xxx 110000h 088000h 64/32 10ffffh 087fffh fsa16 010000xxx 100000h 080000h 64/32 0fffffh 07ffffh fsa15 001111xxx 0f0000h 078000h 64/32 0effffh 077fffh fsa14 001110xxx 0e0000h 070000h 64/32 0dffffh 06ffffh fsa13 001101xxx 0d0000h 068000h 64/32 0cffffh 067fffh fsa12 001100xxx 0c0000h 060000h 64/32 0bffffh 05ffffh fsa11 001011xxx 0b0000h 058000h 64/32 0affffh 057fffh fsa10 001010xxx 0a0000h 050000h 64/32 09ffffh 04ffffh fsa9 001001xxx 090000h 048000h 64/32 08ffffh 047fffh fsa8 001000xxx 080000h 040000h 64/32 07ffffh 03ffffh fsa7 000111xxx 070000h 038000h 64/32 06ffffh 037fffh fsa6 000110xxx 060000h 030000h 64/32 05ffffh 02ffffh fsa5 000101xxx 050000h 028000h 64/32 04ffffh 027fffh fsa4 000100xxx 040000h 020000h 64/32 03ffffh 01ffffh fsa3 000011xxx 030000h 018000h 64/32 02ffffh 017fffh fsa2 000010xxx 020000h 010000h 64/32 01ffffh 00ffffh fsa1 000001xxx 010000h 008000h 64/32 00ffffh 007fffh fsa0 000000xxx 000000h 000000h
data sheet m14923ej4v0ds 8 mc-222262-x sector group address table (flash memory) sector group a20 a19 a18 a17 a16 a15 a14 a13 a12 size sector sga0 000000 64k bytes (1 sector) fsa0 sga1 000001 192k bytes (3 sectors) fsa1?fsa3 10 11 sga2 0 0 0 1 256k bytes (4 sectors) fsa4?fsa7 sga3 0 0 1 0 256k bytes (4 sectors) fsa8?fsa11 sga4 0 0 1 1 256k bytes (4 sectors) fsa12?fsa15 sga5 0 1 0 0 256k bytes (4 sectors) fsa16?fsa19 sga6 0 1 0 1 256k bytes (4 sectors) fsa20?fsa23 sga7 0 1 1 0 256k bytes (4 sectors) fsa24?fsa27 sga8 0 1 1 1 256k bytes (4 sectors) fsa28?fsa31 sga9 1 0 0 0 256k bytes (4 sectors) fsa32?fsa35 sga10 1 0 0 1 256k bytes (4 sectors) fsa36?fsa39 sga11 1 0 1 0 256k bytes (4 sectors) fsa40?fsa43 sga12 1 0 1 1 256k bytes (4 sectors) fsa44?fsa47 sga13 1 1 0 0 256k bytes (4 sectors) fsa48?fsa51 sga14 1 1 0 1 256k bytes (4 sectors) fsa52?fsa55 sga15 1 1 1 0 256k bytes (4 sectors) fsa56?fsa59 sga16 111100 192k bytes (3 sectors) fsa60?fsa62 01 10 sga17 1111110008k bytes (1 sector)fsa63 sga18 1111110018k bytes (1 sector)fsa64 sga19 1111110108k bytes (1 sector)fsa65 sga20 1111110118k bytes (1 sector)fsa66 sga21 1111111008k bytes (1 sector)fsa67 sga22 1111111018k bytes (1 sector)fsa68 sga23 1111111108k bytes (1 sector)fsa69 sga24 1111111118k bytes (1 sector)fsa70 remark : v ih or v il !
data sheet m14923ej4v0ds 9 mc-222262-x command sequence (flash memory) command sequence bus 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle cycle address data address data address data address data address data address data read / reset note1 1 hf0hrard???????? read / reset note1 byte mode 3 aaah aah 555h 55h aaah f0h ra rd ? ? ? ? word mode 555h 2aah 555h program byte mode 4 aaah aah 555h 55h aaah a0h pa pd ? ? ? ? word mode 555h 2aah 555h program suspend note 2 1bab0h?????????? program resume note 3 1ba30h?????????? chip erase byte mode 6 aaah aah 555h 55h aaah 80h aaah aah 555h 55h aaah 10h word mode 555h 2aah 555h 555h 2aah 555h sector erase byte mode 6 aaah aah 555h 55h aaah 80h aaah aah 555h 55h fsa 30h word mode 555h 2aah 555h 555h 2aah sector erase suspend note 4 1bab0h?????????? sector erase resume note 5 1ba30h?????????? unlock bypass set byte mode 3 aaah aah 555h 55h aaah 20h ?????? word mode 555h 2aah 555h unlock bypass program note 6 2 ha0hpapd???????? unlock bypass reset note 6 2 ba 90h h 00h note11 ???????? product id byte mode 3 aaah aah 555h 55h (ba) 90h ia id ? ? ? ? aaah word mode 555h 2aah (ba) 555h sector group protection note 7 4 h 60h spa 60h spa 40h spa sd ? ? ? ? sector group unprotect note 8 4 h 60h sua 60h sua 40h sua sd ? ? ? ? query note 9 byte mode1aah98h?????????? word mode 55h extra one time protect byte mode 3 aaah aah 555h 55h aaah 88h ?????? sector entry word mode 555h 2aah 555h extra one time protect byte mode 4 aaah aah 555h 55h aaah a0h pa pd ? ? ? ? sector program note 10 word mode 555h 2aah 555h extra one time protect byte mode 6 aaah aah 555h 55h aaah 80h aaah aah 555h 55h eotpsa 30h sector erase note 10 word mode 555h 2aah 555h 555h 2aah extra one time protect byte mode 4 aaah aah 555h 55h aaah 90h xxxh 00h ? ? ? ? sector reset note 10 word mode 555h 2aah 555h extra one time protect sector 4 h 60h eotpsa 60h eotpsa 40h eotpsa sd ? ? ? ? protection note 10
data sheet m14923ej4v0ds 10 mc-222262-x notes 1. both these read / reset commands reset the device to the read mode. 2. programming is suspended if b0h is input to the bank address being programmed to in a program operation. 3. programming is resumed if 30h is input to the bank address being suspended to in a program-suspend operation. 4. erasure is suspended if b0h is input to the bank address being erased in a sector erase operation. 5. erasure is resumed if 30h is input to the bank address being suspended in a sector-erase-suspend operation. 6. valid only in the unlock bypass mode. 7. valid only when /reset = v id (except in the extra one time protect sector mode). 8. the command sequence that protects a sector group is excluded. 9. only a0 to a6 are valid as an address. 10. valid only in the extra one time protect sector mode. 11. this command can be used even if this data is f0h. remarks 1. specify address 555h or 2aah (a10 to a0) in the word mode, and aaah or 555h (a10 to a0, a-1) in the byte mode. 2. ra : read address rd : read data ia : address input xx00h (to read the manufacturer code) xx02h (to read the device code in the byte mode) xx01h (to read the device code in the word mode) id : code output. refer to the product id code (manufacturer code / device code) (flash memory) . pa : program address pd : program data fsa: erase sector address. the sector to be erased is selected by the combination of this address. refer to the sector organization / sector address table (flash memory) . ba : bank address. refer to the sector organization / sector address table (flash memory) . spa : sector group address to be protected. set sector group address (sga) and (a6, a1, a0) = (v il , v ih , v il ). for the sector group address, refer to the sector group address table (flash memory) . sua : unprotect sector group address. set sector group address (sga) and (a6, a1, a0) = (v ih , v ih , v il ). for the sector group address, refer to the sector group address table (flash memory) . sd : data for verifying whether sector groups read from the address specified by spa, sua, and eotpsa are protected. eotpsa : extra one time protect sector area addresses. byte mode : 3f0000h to 3fffffh, word mode : 1f8000h to 1fffffh 3. the sector group address is don't care except when a program / erase address or read address are selected. 4. for the operation of the bus, refer to bus operations table . 5. of address bit indicates v ih or v il . 6. refer to dual operation flash memory 32m bits a series information (m14914e) for commands of flash memory. ! ! !
data sheet m14923ej4v0ds 11 mc-222262-x product id code (manufacturer code / device code) (flash memory) product id code address inputs output a6 a1 a0 hex manufacturer code l l l 10h device code l l h 55h (byte mode), 2255h (word mode) product id code code outputs i/o 15 i/o 14 i/o 13 i/o 12 i/o 11 i/o 10 i/o 9 i/o 8 i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 hex manufacturer code 0000000000010000 10h device codebyte modea-1xxxxxxx010 10101 55h word mode0010001001010101 2255h remark h : v ih , l : v il , x : hi-z hardware sequence flags, hardware data protection (flash memory) refer to dual operation flash memory 32m bits a series information (m14914e). !
data sheet m14923ej4v0ds 12 mc-222262-x electrical specifications before turning on power, input v ss 0.2 v to the /reset pin until v cc f v cc f (min.). absolute maximum ratings parameter symbol condition rating unit supply voltage v cc f, v cc s with respect to v ss ?0.5 to +4.0 v input / output voltage v t with respect /wp(acc), /reset ?0.5 note 1 to +13.0 v to v ss except /wp(acc), /reset ?0.5 note 1 to v cc f, v cc s + 0.4 (4.0 v max.) note 2 ambient operation t a ?25 to +85 c temperature storage temperature t stg ?55 to +125 c notes 1. ?2.0 v (min.) (pulse width 20 ns) 2. v cc f, v cc s + 0.5 v (max.) (pulse width 20 ns) caution exposing the device to stress above those listed in absolute maximum rating could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter symbol condition min. typ. max. unit supply voltage v cc f, v cc s2.73.6v ambient operation temperature t a ?25 +85 c
data sheet m14923ej4v0ds 13 mc-222262-x dc characteristics (recommended operating conditions unless otherwise noted) common parameter symbol test condition min. typ. max. unit high level input voltage v ih 2.4 v cc f, v cc s + 0.3 v low level input voltage v il ? 0.3 +0.5 v high level output voltage v oh i oh = ? 500 a, v cc f = v cc f (min.), 2.4 v v cc s = v cc s (min.) low level output voltage v ol i ol = +1.0 ma, v cc f = v cc f (min.), 0.4 v v cc s = v cc s (min.) input leakage current i li ? 1.0 +1.0 a output leakage current i lo ? 1.0 +1.0 a flash memory parameter symbol test condition min. typ. max. unit power read byte mode i cc1 fv cc f = v cc f (max.), t cycle = 5 mhz 10 16 ma supply /cef = v il , /oe = v ih t cycle = 1 mhz 2 4 current word mode t cycle = 5 mhz 10 16 t cycle = 1 mhz 2 4 program, erase i cc2 fv cc f = v cc f (max.), /cef = v il , /oe = v ih 15 30 ma standby i cc3 fv cc f = v cc f (max.), /cef = /reset = 0.2 5 a /wp(acc) = v cc f 0.3 v, /oe = v il standby / reset i cc4 fv cc f = v cc f (max.), /reset = v ss 0.2 v 0.2 5 a automatic sleep mode i cc5 fv ih = v cc f 0.2 v, v il = v ss 0.2 v 0.2 5 a read during programming i cc6 fv ih = v cc f 0.2 v, v il = v ss 0.2 v 21 45 ma read during erasing i cc7 fv ih = v cc f 0.2 v, v il = v ss 0.2 v 21 45 ma programming i cc8 f/cef = v il , /oe = v ih ,1735ma during suspend automatic programming during suspend accelerated i acc /wp (acc) pin 5 10 ma programming v cc f1530 /reset high level input voltage v id high voltage is applied 11.5 12.5 v accelerated programming voltage v acc high voltage is applied 8.5 9.5 v low v cc f lock-out voltage note v lko 1.7 v note when v cc f is equal to or lower than v lko , the device ignores all write cycles. refer to dual operation flash memory 32m bits a series information (m14914e). sram parameter symbol test condition min. typ. max. unit power supply current i cc1s /ce1s = v il , ce2s = v ih , minimum cycle time, i i/o = 0 ma ? 50 ma /ce1s = v il , ce2s = v ih , i i/o = 0 ma, cycle time = ?12 i cc2s /ce1s 0.2 v, ce2s v cc s ? 0.2 v, cycle time = 1 s, ? 10 i i/o = 0 ma, v il 0.2 v, v ih v cc s ? 0.2 v standby supply current i sb1s /ce1s = v ih or ce2s = v il or /lb = /ub = v ih ?0.6ma i sb2s /ce1s v cc s ? 0.2 v, ce2s v cc s ? 0.2 v 1 15 a ce2s 0.2 v 1 15 /lb = /ub v cc s ? 0.2 v, /ce1s 0.2 v, ce2s v cc s ? 0.2 v 1 15 !
data sheet m14923ej4v0ds 14 mc-222262-x ac characteristics (recommended operating conditions unless otherwise noted) ac test conditions flash memory input waveform (rise and fall time 5 ns) test points v ss 3.0 v 1.5 v 1.5 v output waveform test points 1.5 v 1.5 v output load 1 ttl + 30 pf sram input waveform (rise and fall time 5 ns) test points v cc s x 0.9 v v cc s x 0.1 v v cc s / 2 v v cc s / 2 v output waveform test points v cc s / 2 v v cc s / 2 v output load 1 ttl + 30 pf /cef, /ce1s, ce2s timing parameter symbol test condition min. typ. max. unit notes /cef, /ce1s, ce2s recover time t ccr 0ns !
data sheet m14923ej4v0ds 15 mc-222262-x read cycle (flash memory) parameter symbol test condition min. typ. max. unit notes read cycle time t rc 85 ns address access time t acc /cef = /oe = v il 85 ns /cef access time t cef /oe = v il 85 ns /oe access time t oe /cef = v il 40 ns output disable time t df /oe = v il or /cef = v il 30 ns output hold time t oh 0ns /reset pulse width t rp 500 ns /reset hold time before read t rh 50 ns /reset low to read mode t ready 20 s /cef low to ciof low, high t elfl /t elfh 5ns ciof low output disable time t flqz 30 ns ciof high access time t fhqv 85 ns remark t df is the time from inactivation of /cef or /oe to hi-z state output.
data sheet m14923ej4v0ds 16 mc-222262-x write cycle (program / erase) (flash memory) parameter symbol min. typ. max. unit notes write cycle time t wc 85 ns address setup time (/we to address) t as 0ns address setup time (/cef to address) t as 0ns address hold time (/we to address) t ah 45 ns address hold time (/cef to address) t ah 45 ns input data setup time t ds 35 ns input data hold time t dh 0ns /oe hold time read t oeh 0ns toggle bit, data polling 10 read recovery time before write (/oe to /cef) t ghel 0ns read recovery time before write (/oe to /we) t ghwl 0ns /we setup time (/cef to /we) t ws 0ns /cef setup time (/we to /cef) t cs 0ns /we hold time (/cef to /we) t wh 0ns /cef hold time (/we to /cef) t ch 0ns write pulse width t wp 35 ns /cef pulse width t cp 35 ns write pulse width high t wph 30 ns /cef pulse width high t cph 30 ns byte programming operation time t bpg 9 200 s word programming operation time t wpg 11 200 s sector erase operation time t ser 0.7 5 s 1 v cc f setup time t vcs 50 s ry (/by) recovery time t rb 0ns /reset pulse width t rp 500 ns /reset high-voltage (v id ) hold time from high of ry(/by) t rrb 20 s when sector group is temporarily unprotect /reset hold time t rh 50 ns from completion of automatic program / erase to data t eoe 85 ns output time ry (/by) delay time from valid program or erase operation t busy 90 ns address setup time to /oe low in toggle bit t aso 15 ns address hold time to /cef or /oe high in toggle bit t aht 0ns /cef pulse width high for toggle bit t ceph 20 ns /oe pulse width high for toggle bit t oeph 20 ns voltage transition time t vlht 4 s2 rise time to v id (/reset) t vidr 500 ns 3 rise time to v acc (/wp(acc)) t vaccr 500 ns 2 erase timeout time t tow 50 s4 erase suspend transition time t spd 20 s4 notes 1. the preprogramming time prior to the erase operation is not included. 2. sector group protection and accelerated mode only 3. sector group protection only. 4. table only.
data sheet m14923ej4v0ds 17 mc-222262-x write operation (program / erase) performance (flash memory) parameter description min. typ. max. unit sector erase time excludes programming time prior to erasure 0.7 5 s chip erase time excludes programming time prior to erasure 50 s byte programming time excludes system-level overhead 9 200 s word programming time excludes system-level overhead 11 200 s chip programming time excludes system-level overhead byte mode 40 s word mode 25 accelerated programming time excludes system-level overhead 7 150 s erase / program cycle 100,000 cycles
data sheet m14923ej4v0ds 18 mc-222262-x read cycle (sram) parameter symbol min. max. unit notes read cycle time t rc 70 ns address access time t aa 70 ns /ce1s access time t co1 70 ns ce2s access time t co2 70 ns /oe to output valid t oe 35 ns /lb, /ub to output valid t ba 70 ns output hold from address change t oh 10 ns /ce1s to output in low-z t lz1 10 ns ce2s to output in low-z t lz2 10 ns /oe to output in low-z t olz 0ns /lb, /ub to output in low-z t blz 10 ns /ce1s to output in hi-z t hz1 25 ns ce2s to output in hi-z t hz2 25 ns /oe to output in hi-z t ohz 25 ns /lb, /ub to output in hi-z t bhz 25 ns write cycle (sram) parameter symbol min. max. unit notes write cycle time t wc 70 ns /ce1s to end of write t cw1 55 ns ce2s to end of write t cw2 55 ns /lb, /ub to end of write t bw 55 ns address valid to end of write t aw 55 ns address setup time t as 0ns write pulse width t wp 50 ns write recovery time t wr 0ns data valid to end of write t dw 30 ns data hold time t dh 0ns /we to output in hi-z t whz 25 ns output active from end of write t ow 5ns
data sheet m14923ej4v0ds 19 mc-222262-x low v cc data retention characteristics (sram) parameter symbol test condition min. typ. max. unit data retention supply voltage v ccdr1 /ce1s v cc s ? 0.2 v, ce2s v cc s ? 0.2 v 1.0 3.6 v v ccdr2 ce2s 0.2 v 1.0 3.6 v ccdr3 /lb = /ub v cc s ? 0.2 v, 1.0 3.6 /ce1s 0.2 v, ce2s v cc s ? 0.2 v data retention supply current i ccdr1 v cc s = 1.5 v, /ce1s v cc s ? 0.2 v, 0.5 6 a ce2s v cc s ? 0.2 v i ccdr2 v cc s = 1.5 v, ce2s 0.2 v 0.5 6 i ccdr3 v cc s = 1.5 v, /lb = /ub v cc s ? 0.2 v, 0.5 6 /ce1s 0.2 v, ce2s v cc s ? 0.2 v chip deselection to data retention mode t cdr 0ns operation recovery time t r t rc note ns note t rc : read cycle time
data sheet m14923ej4v0ds 20 mc-222262-x figure 1. alternating sram to flash memory timing chart /cef (input) /ce1s (input) ce2s (input) t ccr t ccr t ccr t ccr figure 2. read cycle timing chart 1 (flash memory) address (input) /cef (input) /oe (input) /we (input) hi-z data out t oeh t oh t oe t cef t rc t acc t df hi-z i/o (output) figure 3. read cycle timing chart 2 (flash memory) address (input) /reset (input) t acc hi-z data out hi-z i/o (output) t rc /cef (input) t rh t rp t oh t cef t ready
data sheet m14923ej4v0ds 21 mc-222262-x figure 4. sector group protection timing chart (flash memory) sgax sgax address (input) a0 (input) a1 (input) a6 (input) /cef (input) /reset (input) v cc f /oe (input) /we (input) i/o (input/output) t wc t vcs t vlht t vidr t wc t oe timeout t wp sgay 60h 60h 40h 01h note 60h v id v ih note the sector group protection verification result is output. 01h : the sector group is protected. 00h : the sector group is not protected. figure 5. temporary sector group unprotect timing chart (flash memory) /reset (input) v cc f /we (input) /cef (input) ry (/by) (output) v id v ih t vlht t vcs t vidr t rrb t vlht t vlht (program or erase command sequence) period during which protection is canceled
data sheet m14923ej4v0ds 22 mc-222262-x figure 6. accelerated mode timing chart (flash memory) /wp (acc) (input) v cc f /we (input) /cef (input) ry (/by) (output) v acc v ih t vlht t vcs t vaccr t vlht t vlht (program or erase command sequence) accelerated mode period figure 7. dual operation timing chart (flash memory) address (input) /cef (input) /oe (input) /we (input) i/o (input / output) t as ba1 t rc t ah input output output ba2 ba1 ba2 ba1 ba2 t wc t rc t wc t rc t wc t acc t cef t ceph t aht t as t oe t df t wp t ghwl t ds t dh t df t oeh input output status
data sheet m14923ej4v0ds 23 mc-222262-x figure 8. write cycle timing chart (/we controlled) (flash memory) address (input) /cef (input) /oe (input) /we (input) i/o (input / output) t ds t dh t ghwl t cs t wph t bpg or t wpg t wc t as t ah t ch pd /i/o7 d out t oh t oe t cef t rc 555h pa pa a0h (3rd and 4th write cycle) d out t wp (data polling) remarks 1. this timing chart shows the last two write cycles among the program command sequence's four write cycles, and data polling. 2. this timing chart shows the word mode ? s case. in the byte mode, address to be input are different from the word mode. see command sequence (flash memory) . 3. pa : program address pd : program data /i/o7 : the output of the complement of the data written to the device. d out : the output of the data written to the device. figure 9. write cycle timing chart (/cef controlled) (flash memory) address (input) /cef (input) /oe (input) /we (input) i/o (input / output) t ds t ghel t ws t bpg or t wpg t wc t as t ah pd /i/o7 d out t oh t oe t cef t rc 555h pa pa a0h (3rd and 4th write cycle) d out t wh t dh t cp t cph (data polling) remarks 1. this timing chart shows the last two write cycles among the program command sequence's four write cycles, and data polling. 2. this timing chart shows the word mode ? s case. in the byte mode, address to be input are different from the word mode. see command sequence (flash memory) . 3. pa : program address pd : program data /i/o7 : the output of the complement of the data written to the device. d out : the output of the data written to the device.
data sheet m14923ej4v0ds 24 mc-222262-x figure 10. sector / chip erase timing chart (flash memory) address (input) /cef (input) /oe (input) /we (input) i/o (input) v cc f t ds t dh t ch t cs t wph 555h t wc t as t ah t wp 55h aah 80h aah 55h (10h for chip erase) 30h 2aah 555h 555h 2aah fsa note t ghwl t vcs note fsa is the sector address to be erased. in the case of chip erase, input 555h (word mode), aaah (byte mode). remark this timing chart shows the word mode ? s case. in the byte mode, address to be input are different from the word mode. see command sequence (flash memory) .. figure 11. data polling timing chart (flash memory) /cef (input) t oeh t oe t bpg, t wpg, t ser t cef hi-z t ch /oe (input) /we (input) i/o7 (output) ry (/by) (output) t eoe /i/o7 valid data hi-z i/o0 - i/o6 (output) t df t busy d out note status data note i/o7 = d out : true value of program data (indicates completion of automatic program / erase)
data sheet m14923ej4v0ds 25 mc-222262-x figure 12. toggle bit timing chart (flash memory) /oe (input) /we (input) /cef (input) address (input) i/o6, i/o2 (input / output) t as t aso t aht t aht t ceph t oeph t oeh t busy t dh t oeh t cef t oe input data toggle toggle valid data out stop toggling note toggle ry (/by) (output) note i/o6 stops the toggle (indicates automatic program / erase completion). figure 13. i/o2 vs. i/o6 timing chart (flash memory) /we (input) input of automatic erase command erase suspended erasure resumed erase suspended input of program command erase suspended input of program command erase suspended read erase suspended read erasure erasure completion of erasure toggle i/o6 (output) i/o2 (output) i/o2 and i/o6 (/cef or /oe is used for toggle) figure 14. ry (/by) (ready / busy) timing chart (flash memory) /cef (input) /we (input) ry (/by) (output) t busy automatic program or erase rising edge of the last write pulse figure 15. /reset and ry (/by) timing chart (flash memory) /we (input) /reset (input) ry (/by) (output) t rp t ready t rb
data sheet m14923ej4v0ds 26 mc-222262-x figure 16. write ciof timing chart (flash memory) /cef, /we (input) ciof (input) input determined t ah t as falling edge of last write pulse figure 17. byte mode switching timing chart (flash memory) /cef (input) ciof (input) i/o0 - i/o14 (output) hi-z i/o15 (output), a ? 1 (input) t elfl t acc t flqz hi-z hi-z data output i/o0-i/o14 data output i/o15 data output i/o0-i/o7 address input a ? 1 figure 18. word mode switching timing chart (flash memory) data output i/o15 /cef (input) ciof (input) i/o0 - i/o14 (output) i/o15 (output), a ? 1 (input) t elfh t fhqv t cef hi-z hi-z hi-z data output i/o0-i/o14 data output i/o0-i/o7 address input a ? 1 ! !
data sheet m14923ej4v0ds 27 mc-222262-x figure 19. read cycle timing chart (sram) t hz2 t rc t oh t hz1 t blz t ba t lz2 t co2 t lz1 t co1 t bhz t aa hi-z data out /lb, /ub (input) ce2s (input) /ce1s (input) address (input) i/o (output) t olz t oe t ohz /oe (input) remark in read cycle, /we should be fixed to high level.
data sheet m14923ej4v0ds 28 mc-222262-x figure 20. write cycle timing chart 1 (/we controlled) (sram) t wc t cw1 t bw t whz t dw t dh t ow indefinite data out hi-z hi-z data in indefinite data out address (input) /ce1s (input) /lb, /ub (input) i/o (input / output) ce2s (input) t cw2 t aw t wp t as t wr /we (input) cautions 1. during address transition, at least one of pins /ce1s, ce2s, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. remarks 1. write operation is done during the overlap time of a low level /ce1s, /we, /lb and/or /ub, and a high level ce2s. 2. if /ce1s changes to low level at the same time or after the change of /we to low level, or if ce2s changes to high level at the same time or after the change of /we to low level, the i/o pins will remain hi-z state. 3. when /we is at low level, the i/o pins are always hi-z. when /we is at high level, read operation is executed. therefore /oe should be at high level to make the i/o pins hi-z.
data sheet m14923ej4v0ds 29 mc-222262-x figure 21. write cycle timing chart 2 (/ce1s controlled) (sram) t wc t as t cw1 t dw t dh data in hi-z address (input) /ce1s (input) /lb, /ub (input) i/o (input) hi-z ce2s (input) t cw2 t aw t wp t wr /we (input) t bw cautions 1. during address transition, at least one of pins /ce1s, ce2s, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. remark write operation is done during the overlap time of a low level /ce1s, /we, /lb and/or /ub, and a high level ce2s.
data sheet m14923ej4v0ds 30 mc-222262-x figure 22. write cycle timing chart 3 (ce2s controlled) (sram) t wc t as t cw2 t bw t dw t dh data in hi-z address (input) ce2s (input) /lb, /ub (input) i/o (input) hi-z /ce1s (input) t cw1 t aw t wp t wr /we (input) cautions 1. during address transition, at least one of pins /ce1s, ce2s, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. remark write operation is done during the overlap time of a low level /ce1s, /we, /lb and/or /ub, and a high level ce2s.
data sheet m14923ej4v0ds 31 mc-222262-x figure 23. write cycle timing chart 4 (/lb, /ub controlled) (sram) t wc t dw t dh data in hi-z address (input) /lb, /ub (input) i/o (input) hi-z ce2s (input) t cw2 t aw t wp t wr /we (input) t as t bw /ce1s (input) t cw1 cautions 1. during address transition, at least one of pins /ce1s, ce2s, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. remark write operation is done during the overlap time of a low level /ce1s, /we, /lb and/or /ub, and a high level ce2s.
data sheet m14923ej4v0ds 32 mc-222262-x figure 24. data retention timing chart 1 (/ce1s controlled) (sram) v ih (min.) v ccdr (min.) v il (max.) /ce1s /ce1s v cc s ? 0.2 v v ss v cc s v cc s(min.) t cdr data retention mode t r remark on the data retention mode by controlling /ce1s, the input level of ce2s must be v cc s ? 0.2 v or 0.2 v. the other pins (address, i/o, /we, /oe, /lb, /ub) can be in hi-z state. figure 25. data retention timing chart 2 (ce2s controlled) (sram) v ih (min.) v ccdr (min.) v il (max.) ce2s ce2s 0.2 v v ss t cdr data retention mode t r v cc s v cc s(min.) remark on the data retention mode by controlling ce2s, the other pins (/ce1s, address, i/o, /we, /oe, /lb, /ub) can be in hi-z state.
data sheet m14923ej4v0ds 33 mc-222262-x figure 26. data retention timing chart 3 (/lb, /ub controlled) (sram) t cdr data retention mode v ih (min.) v ccdr (min.) v il (max.) t r /lb, /ub /lb, /ub v cc s ? 0.2 v v ss v cc s v cc s(min.) remark on the data retention mode by controlling /lb and /ub, the input level of /ce1s and ce2s must be v cc s ? 0.2 v or 0.2 v. the other pins (address, i/o, /we, /oe) can be in hi-z state. flow charts (flash memory) refer to dual operation flash memory 32m bits a series information (m14914e). !
data sheet m14923ej4v0ds 34 mc-222262-x cfi code list (1/2) address a6 to a0 data i/o15 to i/o0 description 10h 0051h "qry" (ascii code) 11h 0052h 12h 0059h 13h 0002h main command set 14h 0000h 2 : amd/fj standard type 15h 0040h start address of primary table 16h 0000h 17h 0000h auxiliary command set 18h 0000h 00h : not supported 19h 0000h start address of auxiliary algorithm table 1ah 0000h 1bh 0027h minimum v cc f voltage (program / erase) i/o7 to i/o4 : 1 v/bit i/o3 to i/o0 : 100 mv/bit 1ch 0036h maximum v cc f voltage (program / erase) i/o7 to i/o4 : 1 v/bit i/o3 to i/o0 : 100 mv/bit 1dh 0000h minimum v pp voltage 1eh 0000h maximum v pp voltage 1fh 0004h typical word program time (2 n s) 20h 0000h typical buffer program time (2 n s) 21h 000ah typical sector erase time (2 n ms) 22h 0000h typical chip erase time (2 n ms) 23h 0005h maximum word program time (typical time 2 n ) 24h 0000h maximum buffer program time (typical time 2 n ) 25h 0004h maximum sector erasing time (typical time 2 n ) 26h 0000h maximum chip erasing time (typical time 2 n ) 27h 0016h capacity (2 n bytes) 28h 0002h i/o information 29h 0000h 2 : 8/ 16-bit organization 2ah 0000h maximum number of bytes when two banks are programmed (2 n ) 2bh 0000h 2ch 0002h type of erase block 2dh 0007h information about erase block 1 2eh 0000h bit0 to 15 : y = number of sectors 2fh 0020h bit16 to 31 : z = size 30h 0000h (z 256 bytes)
data sheet m14923ej4v0ds 35 mc-222262-x (2/2) address a6 to a0 data i/o15 to i/o0 description 31h 003eh information about erase block 2 32h 0000h bit0 to 15 : y = number of sectors 33h 0000h bit16 to 31 : z = size 34h 0001h (z 256 bytes) 40h 0050h "pri" (ascii code) 41h 0052h 42h 0049h 43h 0031h main version (ascii code) 44h 0032h minor version (ascii code) 45h 0000h address during command input 00h : necessary 01h : unnecessary 46h 0002h temporary erase suspend function 00h : not supported 01h : read only 02h : read / program 47h 0001h sector group protection 00h : not supported 01h : supported 48h 0001h temporary sector group protection 00h : not supported 01h : supported 49h 0004h sector group protection algorithm 4ah 00xxh number of sectors of bank 2 00h : not supported 38h : mc-222262-x 4bh 0000h burst mode 00h : not supported 4ch 0000h page mode 00h : not supported 4dh 0085h minimum v acc voltage i/o7 to i/o4 : 1 v/bit i/o3 to i/o0 : 100 mv/bit 4eh 0095h maximum v acc voltage i/o7 to i/o4 : 1 v/bit i/o3 to i/o0 : 100 mv/bit 4fh 00xxh boot organization 03h : top boot 50h 0001h temporary program suspend function 00h : not supported 01h : supported
data sheet m14923ej4v0ds 36 mc-222262-x package drawing 77-pin tape fbga (12x7) s x e ab m s wb w sa s y s y1 item millimeters d 12.0 0.1 7.0 0.1 e 0.2 b 0.45 0.05 x 0.08 y 0.1 y1 0.1 zd 0.7 ze 0.8 w a 1.1 0.1 a1 0.26 0.05 a2 0.84 p77f9-80-bt3 b ? index mark a 0.8 e a1 a2 s a b zd ze pnmlkjhgf edcba 8 7 6 5 4 3 2 1 d e
data sheet m14923ej4v0ds 37 mc-222262-x recommended soldering conditions please consult with our sales offices for soldering conditions of the mc-222262-x. type of surface mount device mc-222262f9-bt3 : 77-pin tape fbga (12 7)
data sheet m14923ej4v0ds 38 mc-222262-x revision history edition/ page type of location description date this previous revision (previous edition this edition) edition edition 4th edition/ throughout throughout modification preliminary data sheet data sheet march 2002 ? p.5, 6 deletion contents p.5 p.7 addition bus operations table remark 3 ? p.7 to 9 deletion 1. bus operations, explanation p.12 to 19 3. commands, p.20 to 22 4. hardware sequence flags, p.23 5. hardware data protection p.8 ? addition sector group address table p.10 p.13 modification command sequence remark 2: spa, sua addition remark 6 p.11 ? addition reference comment of information p.12 p.24 deletion electrical specifications capacitance p.13 p.25 modification dc characteristics (flash memory) note: reference comment of information p.14 p.26 modification ac test conditions divided flash memory and sram p.26 p.38 modification figure 17 range of t acc figure 18 range of t cef and t fhqv ? p.46 to 50 deletion 8. flow chart p.33 ? addition reference comment of information
data sheet m14923ej4v0ds 39 mc-222262-x notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
mc-222262-x related documents document name document number dual operation flash memory 32m bits a series information m14914e m8e 00. 4 the information in this document is current as of march, 2002. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ?

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